发明名称 Method and system for using pattern matching to process an integrated circuit design
摘要 Disclosed is a method, system, and computer program product for processing design objects, such as vias, for an integrated circuit design. In one approach, pattern matching is employed to perform DRC/LVS for scattering bars and Vias. A library of via combinations can be used to insert scattering bars into design. This approach of using a library can be applied to other structures in design in addition to vias.
申请公布号 US2006281200(A1) 申请公布日期 2006.12.14
申请号 US20060453720 申请日期 2006.06.14
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 CADOURI EITAN
分类号 H01L21/66;H01L23/58 主分类号 H01L21/66
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