发明名称 MEMORY SYSTEM
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a memory system, which stably operates in a high frequency, has a topology not requiring consideration for an effect caused by a radiation noise, and has a varied wiring topology for data and command address signals. <P>SOLUTION: In the memory system comprising a plurality modules, each of which is provided with a plurality of DRAMs, each of the DRAMs and a memory controller (MC) is connected with a data wiring and clock wiring. The clock wiring has a specific topology for each module in the manner similar to a command address wiring. The data wiring, also, has a topology for connecting a corresponding DRAM on each module. As a result, a clock and command address wiring has a topology, which is shorter than that of the clock wiring. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2006338689(A) 申请公布日期 2006.12.14
申请号 JP20060244432 申请日期 2006.09.08
申请人 ELPIDA MEMORY INC 发明人 MATSUI YOSHINORI
分类号 G06F12/00;G06F1/04;G06F1/18;G06F13/16 主分类号 G06F12/00
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