| 摘要 |
PROBLEM TO BE SOLVED: To provide a design device for realizing the high speed operation of a semiconductor integrated circuit by using a standard cell system. SOLUTION: This design device is provided with a layout storage device 4 for storing the layout of the arrangement of a plurality of first standard cells including laterally adjacent pMOS transistors and nMOS transistors; an analyzing means 12 for analyzing a path for connecting the plurality of first standard cells to each other; and a replacing means 13 for replacing the first standard cells with second standard cells where lateral height is equal to and the rate of the gate width of the pMOS transistors, and the gate width of the nMOS transistors is different from that of the first stand cells based on the analytic result. COPYRIGHT: (C)2007,JPO&INPIT
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