发明名称 SERIAL INTERFACE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To perform high-speed packet communication while avoiding delay based on a busy state of asynchronous communication. SOLUTION: When an asynchronous packet is sent from a transmitting side in step S1 (start), a receiving side receives the asynchronous packet in step S2. If the receiving side is not in a busy state in step S3 (No), an acknowledge complete packet is redirected to the transmitting side (step S4). If the receiving side is in the busy state (Yes), on the other hand, a busy acknowledge is redirected to the transmitting side (step S5). At the transmitting side, "1" is added to (x) in the case of last transmission in step S6, processing is returned to step S2 after waiting for an Nx time in step S7, an asynchronous packet is sent again and at the receiving side, this asynchronous packet is received. The similar processing is continued thereafter until the transmitting side receives an acknowledge complete packet. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006340194(A) 申请公布日期 2006.12.14
申请号 JP20050164384 申请日期 2005.06.03
申请人 SHARP CORP 发明人 SASAKI JUN
分类号 H04L12/28;H04L1/16 主分类号 H04L12/28
代理机构 代理人
主权项
地址