发明名称 |
Circuit simulation method and circuit simulation apparatus |
摘要 |
In designing a semiconductor integrated circuit, circuit information used for circuit simulation is extracted from measurement values of electric characteristics of a device included in TEG and parameters included in a netlist are modified using the measurement values and simulation values. Circuit simulation is carried out using the thus modified netlist to lead to a decrease in error in the circuit simulation which is caused due to difference between design dimension and actual finished dimension, thereby preventing an increase in design margin and a yield lowering by malfunction.
|
申请公布号 |
US2006282249(A1) |
申请公布日期 |
2006.12.14 |
申请号 |
US20060349077 |
申请日期 |
2006.02.08 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
IKOMA DAISAKU;YAMASHITA KYOJI;OOTANI KATSUHIRO |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|