An output buffer circuit is provided to obtain an output voltage having a high slewing rate by adding a flipped voltage follower including a plurality of transistors thereto. An input stage(301a-301c,301e-301f) applies a differential input voltage signal to two input terminals. A class AB output stage(304a,304b) increases a current applied to an output stage when a differential input voltage difference is more than 0. A floating current source(302a-302d) biases the class AB output stage. A summing circuit(303a-303h) is connected with the input stage, the floating current source, and the class AB output stage in order to sum up the current supplied from the input stage and an internal current supplied from the floating current source. A clamp circuit(305a-305d) is connected with the summing circuit and the class AB output stage in order to limit the magnitude of voltage swing. A flipped voltage follower is connected with the input stage and the clamp circuit in order to apply a bias voltage according to a slewing state of the differential input voltage signal.
申请公布号
KR20060127427(A)
申请公布日期
2006.12.13
申请号
KR20050048408
申请日期
2005.06.07
申请人
SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人
PARK, CHAN WOO;CHOI, WON TAE;KIM, BYUNG HOON;LEE, YOUN JOONG