ARITHMETIC CIRCUIT WITH BALANCED LOGIC LEVELS FOR LOW-POWER OPERATION

摘要

An adder circuit comprising a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least give one of the adder stages are substantially balanced in terms of a number of gate delays experienced by said signals within said adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.