发明名称 Reduction of adjacent floating gate data pattern sensitivity
摘要 The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a first memory cell to the reduced floating gate voltage, programs and verifies an adjacent memory cell to the reduced floating gate voltage, and verifies the first memory cell to an increased floating gate voltage that is greater than the reduced floating gate voltage.
申请公布号 US7149117(B2) 申请公布日期 2006.12.12
申请号 US20060403781 申请日期 2006.04.13
申请人 MICRON TECHNOLOGY, INC. 发明人 ROOHPARVAR FRANKIE F.
分类号 G11C16/04 主分类号 G11C16/04
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