发明名称 Method of designing low-power semiconductor integrated circuit
摘要 A branching point on a wire is detected in the layout results S 101 . A delay amount of a route with a dummy buffer being inserted on a wire subsequent to the branching point S 102 and that of the route without a dummy buffer being inserted are then calculated S 103 . Based on the delay amounts, an insertion point at which a load-dividing buffer is to be inserted is determined S 104 . On condition that a load-dividing buffer is to be inserted at the insertion point, the drive capability of a driving cell preceding the insertion point is calculated so that timing constraints are satisfied S 105 . Then, after it is confirmed that a load-dividing buffer is insertable at the determined insertion point S 106 , processes of placing a load-dividing buffer, changing the drive capability of the driving cell, and changing wiring information are performed on the layout results S 107.
申请公布号 US7148135(B2) 申请公布日期 2006.12.12
申请号 US20040815690 申请日期 2004.04.02
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 FUJITA MITSUTOSHI;KONDO SHUJI
分类号 G06F17/50;H01L21/44;G06F9/455;H01L21/82 主分类号 G06F17/50
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