| 摘要 |
A memory circuit includes a latch having a first node and a second node, a word selecting line, a first MIS transistor having the source/drain nodes thereof coupled to the first node and a predetermined node, respectively, and the gate node thereof coupled to the word selecting line, a second MIS transistor having the source/drain nodes thereof coupled to the second node and the predetermined node, respectively, and the gate node thereof coupled to the word selecting line, and a control circuit configured to subject in a write mode, one of the first MIS transistor and the second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, and to subject in a recovery mode both the first MIS transistor and the second MIS transistor for equal amount of time to equal bias conditions that cause a lingering change in transistor characteristics thereof.
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