发明名称 |
Apparatus, method and limited set of messages to transmit data between scheduler and a network processor |
摘要 |
An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.
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申请公布号 |
US7149212(B2) |
申请公布日期 |
2006.12.12 |
申请号 |
US20020095844 |
申请日期 |
2002.03.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CALVIGNAC JEAN LOUIS;HEDDES MARCO;LOGAN JOSEPH FRANKLIN |
分类号 |
H04L12/50;H04L12/56;H04L29/06 |
主分类号 |
H04L12/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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