| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a page buffer circuit capable of reducing its occupied area by using a data verification circuit to execute the program operation of a multilevel cell. <P>SOLUTION: The page buffer circuit of a flash memory device including a plurality of multilevel cells connected to a bit line is provided with a high-order bit register for sensing the voltage of a sensing node to store high-order sensing data, a low-order bit register for sensing the voltage of the sensing node to store first and second low-order sensing data, a high-order bit verification circuit for receiving one of the high-order sensing data and input data and outputting high-order verification data in response to the data, and a low-order verification circuit for receiving the first low-order sensing data or the inverted second low-order sensing data and outputting low-order verification data in response to the received data. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
