| 摘要 |
A method for fabricating a contact plug of a semiconductor device is provided to reduce contact resistance and to improve reliability and yield of a device by using a solid phase epitaxy process. Gates(23) having a spacer(24) are formed on a silicon substrate(21). A junction region(25) is formed on a surface of the substrate at both sides of the gate. An interlayer dielectric(26) is formed on the whole surface of the substrate to cover the gates. The interlayer dielectric is etched to form a contact hole to simultaneously expose the gates and the junction region between the gates. An amorphous silicon is formed on the junction region between the gates exposed by the contact hole through an SPE(Solid Phase Epitaxy) process at 400-700‹C. An upper portion of the amorphous silicon is etched lower than the gate to form a lower contact material(28) on the junction region between the gates. An upper contact material(29) is formed on the resultant structure of the substrate including the lower contact material. The upper contact material is etched to expose the gate.
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