| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To facilitate delay time adjustments by optimizing a clock tree in a clock control circuit for LSI integrating test circuits. <P>SOLUTION: The clock control circuit comprises a system register 21, a memory 22, a scan bypass register 23 and a BIST register 24. Clocks supplied to the registers are selected by a single multiplexer 11. Clock lines for transmitting the clocks to the registers are bundled into a single clock line 30. The multiplexer 11 comprises a first input terminal P1 to which a BIST clock is applied in a BIST mode and a scan clock is applied in a scan mode, and a second terminal P2 to which a system clock is applied. The multiplexer 11 is controlled by the output of an OR circuit 12 into which a BIST mode signal and a scan mode signal are input. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
