Halbleiter-Package, das ein Neuverteilungsmuster enthält, und Verfahren zu dessen Herstellung

摘要

A semiconductor device package has substrate (21); first and second chip pads spaced apart over substrate surface; insulating layer over substrate surface and having stepped upper surface; conductive reference potential line electrically connected to first chip pad; conductive signal line electrically connected to second chip pad; and first and second external terminals. The semiconductor device package comprises substrate; first and second chip pads spaced apart over the substrate surface; insulating layer over the substrate surface, and comprising a stepped upper surface defined by a lower surface portion, and an upper surface portion, in which a thickness of the insulating layer at the lower surface portion is less than a thickness of the insulating layer at the upper support surface portion; conductive reference potential line electrically connected to the first chip pad and substantially located on the lower surface portion of the insulating layer; conductive signal line electrically connected to the second chip pad and substantially located on the upper surface portion; and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively. An independent claim is also included for a method of manufacturing semiconductor device package comprising forming insulating layer over the surface of substrate, in which first and second chip pads are spaced apart over the surface; contouring an upper surface of the insulating layer to obtain stepped upper surface defined by lower and upper surface portions; forming conductive reference potential line on the lower surface portion of the insulating layer which is electrically connected to the first chip pad; forming conductive signal line on the upper surface portion which is electrically connected to the second chip pad; and forming first and second external terminals which are electrically connected to the conductive reference potential line and the conductive signal line, respectively.