| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory control circuit whose effective speed to a volatile memory is increased. SOLUTION: An arbitration circuit 32d arbitrates a refresh request to request the refresh of an SDRAM, a writing request to request the data writing of the SDRAM and a reading request to request the data reading of the SDRAM. A refresh command generator 32i periodically generates a refresh command when the refresh request is approved by the arbitration circuit 32d, and a memory access circuit 32j executes the data writing and the data reading when the writing request and the reading request are approved by the arbitration circuit 32d. A switch SW selects either every 8 pixel clock or every 11 pixel clock as the cycle of the generation of the refresh command by the refresh command generator 32j. COPYRIGHT: (C)2007,JPO&INPIT
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