发明名称 Clock and data timing compensation for receiver
摘要 According to some embodiments, a system provides acquisition of a first sample of a data signal based on a first clock signal associated with a first phase, the first sample associated with a first data eye of a clock cycle, acquisition of a second sample of the data signal based on a second clock signal associated with a second phase, the second sample associated with a second data eye of the clock cycle, determination of whether the first sample reflects expected data associated with the first data eye, control of the first phase of the first clock signal based on whether the first sample reflects the expected data associated with the first data eye, determination of whether the second sample reflects expected data associated with the second data eye, and control of the second phase of the second clock signal based on whether the second sample reflects the expected data associated with the second data eye.
申请公布号 US2006274874(A1) 申请公布日期 2006.12.07
申请号 US20050142764 申请日期 2005.06.01
申请人 KUMAR ARVIND;ANDERSON WARREN R;POWLEY GEORGE S;WIGHT JEFF 发明人 KUMAR ARVIND;ANDERSON WARREN R.;POWLEY GEORGE S.;WIGHT JEFF
分类号 H04L7/04 主分类号 H04L7/04
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