发明名称 CMOS devices for low power integrated circuits
摘要 A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device and thermally oxidizing the MOS device to form a gate dielectric substantially thicker at a gate dielectric edge than that at a gate dielectric center. Embodiments further comprise performing a source/drain ion implant to form an asymmetric source/drain, wherein the source region includes a high leakage source junction, and wherein the drain region includes a low leakage drain junction. Other embodiments of the invention comprise a MOS device formed in a semiconductor substrate, wherein the device has improved resistance to floating body effects. Still other embodiments include a CMOS device for low power integrated circuits.
申请公布号 US2006273391(A1) 申请公布日期 2006.12.07
申请号 US20050142214 申请日期 2005.06.01
申请人 DIAZ CARLOS H;CHANG MI-CHANG 发明人 DIAZ CARLOS H.;CHANG MI-CHANG
分类号 H01L29/76 主分类号 H01L29/76
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