| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit provided with a mechanism for correcting a delay amount to be inserted for ensuring a hold time into an optimum value, while including the case of disconnecting a delay circuit to be inserted, if unnecessary. <P>SOLUTION: The semiconductor integrated circuit includes a control circuit for correcting the hold time in a FF4 arranged at an output side of a combination logic circuit 2 and comprising: a selector 5 that supplies a control signal CTRL for designating a setting delay value and a delay value or the like depending on a measured delay value at a test after the manufacturing and an actual operating condition to a low power optimum delay circuit 3; and the low power optimum delay circuit 3 with a configuration that is inserted in a signal path from a FF1 arranged at an input side of the combination logic circuit 2 to the FF4 arranged at the output side, generates a different delay value according to the instruction of the control signal CTRL and can be escaped from the signal path. Thus, the control circuit can set the delay amount to be inserted for ensuring the hold time to an optimum value and attain low power consumption. <P>COPYRIGHT: (C)2007,JPO&INPIT |
