| 摘要 |
PROBLEM TO BE SOLVED: To mitigate bad influence that indefinite value causes in logic simulation. SOLUTION: By this method, in a higher order level circuit 20 in which one logic circuit is described by two different levels and a lower order level circuit 21, correspondence of a node O in the higher order level circuit 20 with a node F in the lower order level circuit 21 is determined. Because the expected value of a node O is '1' and a node F is indefinite value (X) in logic simulation, when the occurrence of an expected value error node 22 is detected, logic simulations are performed respectively substituting '0' and '1' for an indefinite value node C that becomes cause of the indefinite value (X) of the node F. In both cases, the value of the expected value error node (the indefinite value node) 22 is rewritten to fixed value '1' after it is confirmed that the node F has same value '1'. Thereby, the expected value error between the node O and the node F is dissolved and continuous execution of logic simulation becomes possible. COPYRIGHT: (C)2007,JPO&INPIT
|
