NAND FLASH MEMORY DEVICE HAVING PAGE BUFFER DISCHARGING BIT LINE VOLTAGE DURING ERASE OPERATION

摘要

A NAND flash memory device comprising a page buffer discharging a bit line voltage during the erase operation is provided to prevent breakdown of a transistor in the page buffer, by discharging the bit line voltage increased by capacitance coupling during the erase operation. A first bit line is connected to a cell array. A blocking circuit is connected to the first bit line, and blocks an erase voltage applied to the first bit line from being delivered to a second bit line during the erase operation. A page buffer is connected to the second bit line, and discharges the voltage of the second bit line during the erase operation. The blocking circuit comprises a high voltage transistor(205) having endurance as to the erase voltage applied to the first bit line.