| 摘要 |
An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. The switch units are coupled in series and have the TDI signal and the TCLK signal applied to the first switch unit. In response to first control signals, the switch unit can either transmit the TDI signals applied to the input terminal through the associated TAP unit to a switch unit output terminal or apply TDI signals directly to the output terminal. Similarly, the TCLK signal can be short-circuited across a switch unit or applied to the TAP unit and a RTCLK can controllably applied to the switch unit output terminal. The interface unit includes a logic unit that permits signals from the TAP unit to provide control signals to each of the switch units. The interface unit includes a plurality of status and control registers, the status registers including the power, clock and security status of an associated processor/core. The status of each processor/core is available to the test and debug unit through the TAP unit of the interface unit.
|
