EXTRACTED-INDEX ADDRESSING OF BYTE-ADDRESSABLE MEMORIES

摘要

A microprocessor circuit useful for indexed addressing of byte -addressable memories includes word- length index, base address, and destination registers (Ri, Rb, Rd) designated by an instruction. The instruction also specifies one byte (t, u, l, b) packed within the index register (Ri), which is to be extracted. A multiplexer (15) has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control () passes the specified byte to its output (17). The extracted byte is provided directly at specific bit positions of a zero-extended address offset word (19). The offset word is added (25) to the base address, the sum (ADDR) being used to address memory contents (27) that are loaded into the destination register (Rd).