| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To effectively lower the standby voltage in an SRAM to reduce the leakage current. <P>SOLUTION: This semiconductor memory device has 1st and 2nd additional FETs (N1, P1) added and disposed in parallel on one of the potential lines DL, SL to supply a first and second drive voltages VDD, VSS to each of memory cells 24 in the SRAM. When selecting a memory cell, the selection signal SEL is supplied through the selection signal supply line L1 to the gate terminal of the added first FET (N1) to turn it on. Corresponding to the non-selection or selection of the memory cells, the bias voltage Vbs having a first and second levels is supplied through the bias supply line L2 to the gate terminal of the added second FET (P1). <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
