发明名称 VOLTAGE LEVEL CONVERSION CIRCUIT WITH STABLE TRANSITION DELAY CHARACTERISTIC
摘要 PROBLEM TO BE SOLVED: To provide a voltage level conversion circuit with a stable transition delay characteristic. SOLUTION: A voltage level conversion circuit changes an input signal of a first voltage into an output signal of a second voltage. The circuit includes an input terminal receiving an input signal, an output terminal outputting an output terminal, and first and second level-shifting units connected in parallel between the input and the output terminals. In particular, the first and the second level-shifting units have difference transition delay characteristics, enabling rising and falling transition delays to be variable in the same ratio when the first and the second voltages are changed. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006333466(A) 申请公布日期 2006.12.07
申请号 JP20060135396 申请日期 2006.05.15
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 KIM MIN-SU
分类号 H03K19/0185;H03K5/04 主分类号 H03K19/0185
代理机构 代理人
主权项
地址