Method for improving the data transfer in semi synchronous clock domains integrated circuits at any possible m/n clock ratio

摘要

A method for data transfer between two semi synchronous clock domains in a System on Chip including at least a first and second integrated processors or circuits, respectively working at a first and a second frequency clock comprising a phase for detecting, for each frequency ratio between the first and the second frequency clock, a maximum rate of the data transfer, the rate being function of all the possible input and output delays supported by the System on Chip, depending on a plurality of technological parameters; a phase for programming a Generic Frequency Converter between the first and second integrated processors or circuits for the data transfer; a phase for scheduling the data transfer between the semi synchronous clock domains.