| 摘要 |
A semiconductor device is provided to make a work function between a gate electrode and an n-type cell well have a difference of almost 0 volt by forming a gate lower electrode made of n-type polysilicon and a PMOS cell transistor with a p-type impurity implantation region. An isolation process is performed to form an isolation layer for defining an active region(100a) in a semiconductor substrate(100). Impurities are implanted into the semiconductor substrate to form a cell well region. A predetermined thickness of the isolation layer is etched. A gate oxide layer(170) is formed on the active region. A stack structure of a planarized n-type lower gate electrode layer, a conductive layer for an upper gate electrode and a gate upper insulation layer is formed on the resultant structure. The stack structure is patterned to form a pin-type gate structure(210) composed of an n-type lower gate electrode(180), an upper gate electrode(190) and a gate upper insulation layer pattern(200). P-type impurities are implanted into the semiconductor substrate at both sides of the gate structure to form a p-type impurity implantation region. A p-type contact plug or metal contact plug connected to the p-type impurity implantation region is formed.
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