发明名称 |
Method of testing phase lock loop status during a Serializer/Deserializer internal loopback built-in self-test |
摘要 |
System and method are implemented to allow phase lock loop (PLL) status testing during a Serializer/Deserializer (SERDES) internal loopback built-in self-test (BIST). An existing pseudo random binary sequence (PRBS) data generator is modified to include a mode that produces a data pattern having a frequency content low enough to be verified on the tester used at the probe.
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申请公布号 |
US7146284(B2) |
申请公布日期 |
2006.12.05 |
申请号 |
US20030704288 |
申请日期 |
2003.11.07 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
KO JESSE JONGHYUK;LYTOLLIS SHAUN |
分类号 |
G06F19/00;G01R31/317 |
主分类号 |
G06F19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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