| 摘要 |
A decoding circuit of a flat panel display is provided to reduce the layout area by making the length of a gate of a MOSFET(Metal Oxide Semiconductor Field Effect Transistor) included in a first decoder short. A decoding circuit of a flat panel display comprises a first decoder(100) for selecting a predetermined number of gradation voltages from plural gradation voltages(V1~V32) according to the lowermost data of at least one bit of image data(D1~D5) and outputting the selected gradation voltages; a second decoder(200) for selecting one of the gradation voltages according to plural selection signals and outputting the selected gradation voltage to an output stage(OUT); and a third decoder(300) for outputting plural selection signals according to the uppermost data of at least one bit of the image data. The minimum length of a gate of plural MOSFETs(MLN,MLP) included in the first decoder is shorter than that of plural MOSFETs(MH) included in the second decoder.
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