HIGH-SPEED, LOW-NOISE VOLTAGE-CONTROLLED DELAY CELL

摘要

A high-speed low-noise voltage-controlled delay cell is disclosed. The source of a first and a second transistor are coupled to a first voltage wire. The drains of first and third transistor coupling the gates of second and fourth transistor output a second output signal. The drains of second and fourth transistor coupling the gates of firth and third transistor output a first output signal. The sources of second and fourth transistor are coupled to a second voltage wire. The output ends of first and third converter are coupled to the drain of the first transistor. The output ends of second and fourth converter are coupled to the drain of the second transistor. The input ends of first and second converter receive a first and a second input signal, respectively. The input ends of third and fourth converter receive a control voltage.