| 摘要 |
PROBLEM TO BE SOLVED: To enable high speed by reducing the wiring length in an upper wiring layer and enable miniaturization by realizing further integration in a semiconductor integrated circuit device of a gate array system mounting with an IP. SOLUTION: The device is provided with a semiconductor substrate 11; a plurality of first transistors formed on the semiconductor substrate 11; a gate array section 12 connected to at least a source, a drain and a gate of each of the first transistors, and having a plurality of first wirings formed thereon, thereby forming a circuit having an optional function; and at least one IP (Intellectual Property) section 13 previously having predetermined functions and formed on the semiconductor substrate 11. The IP section 13 is arranged so as to be adjacent to the gate array section 12, has such a shape that its long side is larger than its short side, and a plurality of third wirings are formed along the long side direction on the IP section 13. COPYRIGHT: (C)2007,JPO&INPIT
|
