发明名称 LOGIC VERIFICATION METHOD AND LOGIC VERIFICATION DEVICE
摘要 PROBLEM TO BE SOLVED: To solve the following problem: because unexpected operation or a glitch generated in output causes malfunction in a logic circuit of a following stage in a logic block with two asynchronous signals as input, it is necessary to detect a collision point (the logic block) with the asynchronous signals as the input. SOLUTION: A net list of a logical level is hierarchically developed S-13 to a lower logic circuit, and two signals are set S-14. According to the signal, retrieval S-16 of a second route and retrieval S-15 of a first route including a loop circuit are performed by width preferential retrieval to retrieve the collision point. the signal is replaced, and retrieval S-17 of the first route and retrieval S-18 of the second route are performed to retrieve the collision point. By bringing results thereof together, the high-speed collision point without leakage can be retrieved, and logical operation or operation timing in the collision point can be confirmed. By converting a net list of a transistor level into the net list of the logical level, a circuit of the transistor level can be handled. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006323727(A) 申请公布日期 2006.11.30
申请号 JP20050147777 申请日期 2005.05.20
申请人 ELPIDA MEMORY INC;HITACHI ULSI SYSTEMS CO LTD 发明人 SUZUKI KUNIHIKO;OTA TADASHI
分类号 G06F17/50 主分类号 G06F17/50
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