External clock synchronization semiconductor memory device and method for controlling same

摘要

An external clock synchronization SRAM 1 of one embodiment comprises a SRAM cell, a global digit line, a global precharge circuit, a D latch, and a global precharge control circuit. A delay circuit is disposed in the global precharge control circuit so that the precharge output of the global precharge circuit changes with a delay with respect to the clock signal supplied to the D latch.