发明名称 CLOCK GENERATING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock generating circuit for executing frequency modulation capable of carrying out intended frequency modulation. <P>SOLUTION: The clock generating circuit includes: a phase comparator for receiving a reference clock and a feedback clock; a current controlled oscillator for generating an operating clock on the basis of an output of the phase comparator; a frequency divider circuit for dividing the operating clock at a frequency division rate on the basis of a frequency division rate setting signal to obtain the feedback clock; and a control circuit that counts the number of the operating clocks and outputs a control current setting signal for setting a control current of the current controlled oscillator and the frequency division rate setting signal on the basis of a result of the count. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006324750(A) 申请公布日期 2006.11.30
申请号 JP20050143859 申请日期 2005.05.17
申请人 NEC ELECTRONICS CORP 发明人 HAYASHIDA KEIJI
分类号 H03L7/183;H03L7/099 主分类号 H03L7/183
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