| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To realize a synchronization circuit capable of synchronously operating a plurality of 1: nDEMUXs and n: 1MUX having no reset terminal in parallel. <P>SOLUTION: The synchronization circuit synchronizes operation timings of a plurality of counter ICs receiving an input clock signal to be operated. The circuit is provided with a phase difference detecting means for detecting phase difference between a clock signal of a counter IC means used as a reference and a clock signal of another counter IC means to be synchronized among the plurality of counter IC means; and a phase control means for controlling the phase of the clock signal of the other counter IC means on the basis of the detected phase difference. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
