| 摘要 |
Phased-lock loop (PLL) system and method for compensating current leakage where current leakage may include gate-leak current attributable to a gate capacitor. In particular, providing a compensation current to an input node of a voltage-controlled oscillator (VCO) to substantially compensate current leakage and therefore reduce PLL jitter. The PLL circuit includes a compensation charge pump which receives input from a counter and in turn provides a counter-value-proportional compensation current. The counter value increments and decrements according to up and down inputs from a phase frequency detector. The counter value is fixed when the PLL circuit is locked. The PLL circuit is driven to lock by the compensation charge pump, with or without the aid of another charge pump. While the PLL is locked, the compensation charge pump may provide a fixed counter-value-proportional compensation current.
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