| 摘要 |
A processor 2 incorporates a branch prediction mechanism 14, 18, 20 which acts to predict branch outcomes for predicted type branch instructions. The processor also supports non-predicted type branch instructions which are ignored by the branch prediction mechanisms 14, 18, 20 and are not subject to prediction. The impact of mispredictions degrading overall performance of the prediction mechanisms 14, 18, 20 is reduced by employing non-prediction type branch program instructions to represent/control branch operations when it is known that misprediction is likely for those branch operations.
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