发明名称 Method for abstraction of manufacturing test access and control ports to support automated RTL manufacturing test insertion flow for reusable modules
摘要 A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.
申请公布号 US2006271904(A1) 申请公布日期 2006.11.30
申请号 US20050140392 申请日期 2005.05.27
申请人 LSI LOGIC CORPORATION 发明人 EMERSON STEVEN M.;BYRN JONATHAN W.;GABRIELSON DONALD B.;LIPPERT GARY
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址