| 摘要 |
The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and issues one gated clock to the functional logic. This creates a new CPU state and causes the change signal to toggle, and the trace logic notes the state change in the signal. It then exports the internal state presented to it. Once it completes the export, it changes the state of advance and the process begins anew.
|
