| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a computer device for reducing a delay time in the processing system of an instruction code whose reading from a built-in memory is required at a high speed when realizing an ECC function for reading the instruction code from the memory. <P>SOLUTION: General data having 16 bit length and a high speed non-requirement instruction code are added with parity 5 bits, and a high speed requirement instruction code having 12 bit length is added with parity 9 bits in the form of "4+parity 3 bits"×3, and stored in a built-in memory 2. A conventional type ECC circuit 4 which is generally used is applied to the bit string of "16+parity 5 bits", and an error correction/decoder 14 in which the number of passing stages is reduced is applied to the bit string of "4+parity 3 bits"×3 by sharing error correction and decoding as post-correction processing. Thus, it is possible to read the high speed requirement instruction code from the built-in memory by reducing a delay time. <P>COPYRIGHT: (C)2007,JPO&INPIT |
