| 摘要 |
PROBLEM TO BE SOLVED: To provide a TCP/IP reception processing circuit, etc., capable of reducing the load of creating a logical data stream from a plurality of packets. SOLUTION: The TCP/IP reception processing circuit 5 is provided with a frame analysis processing part 21, an analysis result data storing part 22, an FIFO buffer memory 23, a DMA control part 24 and a DMA processing part 25. The frame analysis processing part 21 performs CRC verification of a frame received from a lower layer, and writes an analysis result in the analysis result data storing part 22 and writes a packet in the FIFO buffer memory 23. The DMA control part 24 controls the DMA processing part 25 so as to transfer the packet in the FIFO buffer memory 23 to a packet storage area formed in a main memory 9 in accordance with a communication end point being a destination of the packet. COPYRIGHT: (C)2007,JPO&INPIT
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