| 摘要 |
There is provided a semiconductor storage device capable of executing a high-speed read operation without increasing a chip area thereof. The semiconductor storage device includes per-bit sensing circuits 103 each connected to a pair of bit lines (BLT, BLN) and a data output circuit 104 connected to the bit lines BLT from the per-bit sensing circuits, for outputting read data. Each of the per-bit sensing circuits 103 includes a pre-charge circuit for setting the bit line pair to a supply voltage VDD when a bit line pair selection signal YS is inactive, a latch circuit for setting the bit line pair to complementary levels (VDD and GND) according to a read signal when the bit line pair selection signal YS and a sensing circuit activation signal SE are active, and a data write circuit connected to a pair of write data lines (WDT, WDN), for setting one of the bit line pair to a second level (GND) according to write data when the bit line pair selection signal is active. The data output circuit 104 includes a logic circuit and an output transistor. The logic circuit outputs a first value when the bit lines are all at a first level (VDD) and outputs a second value when at least one of the bit lines is at the second level. The output transistor outputs read data to a data output line DL based on an output of the logic circuit.
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