LOW-COST, LOW-VOLTAGE SINGLE-LAYER POLYCRYSTALLINE EPPROM MEMORY CELL INTEGRATION INTO BICMOS TECHNOLOGY

摘要

An EEPROM memory transistor (200) has a floating gate (331) that- is formed using a BiCMOS process. A first sinker dopant region (221, 311, 411) is proximate to a tunnel diode window (220, 322, 423) , and a second sinker dopant region (403) is proximate to a coupling capacitor region (230) . An optional third sinker region (309) may be formed proximate to a source junction (209) of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region (240) may be formed between the first and second sinker dopant regions.