| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL frequency setting circuit reduced in scale by utilizing the regularity between a channel number and its frequency setting value. <P>SOLUTION: A quotient and a remainder resulting from subtracting "1" from the channel number CH and dividing the difference of the subtraction by "3" are respectively stored to bits b7 to b3, and bits b1 to b0 of an address corresponding to the channel number CH in a table 20 employing a ROM. When a channel setting section 10 designates the channel number CH, a decoder 30 interprets the values of the bits b1 to b0 read from the table 20 and the result is given to a selector 40 as a selection signal. Thus, the selector 40 selects and outputs a frequency setting value in lower-digit 12 bits. On the other hand, the values of the bits b7 to b3 read from the table 20 are added to an initial value in two middle digits by an adder 50, and a result of the summation is outputted as a frequency setting value in two middle digit 8 bits. <P>COPYRIGHT: (C)2007,JPO&INPIT |
