| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory management device for performing write and read of data and access to a nonvolatile memory under the consideration of priority, and for preventing a slave CPU from being unable to perform access to the memory when a master CPU breaks down. SOLUTION: A master CPU 1 manages access data from a slave CPU 2 side to an EEPROM 3, and when a memory access request is generated from the slave CPU 2, the master CPU 1 side performs access to the EEPROM 3, and executes the transfer of write/read data by DMA communication. Thus, it is possible for a plurality of CPUs to share one EEPROM 3, and to prevent simultaneous access to the EEPROM 3. Also, when the master CPU 1 goes down, or the DMA communication is turned to be abnormal, the slave CPU 2 voluntarily perform access to the EEPROM 3. Thus, it is possible to prevent the slave CPU 2 from being unable to perform memory access. COPYRIGHT: (C)2007,JPO&INPIT
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