| 摘要 |
An integrated circuit device is provided which can increase a stable area having less digital noise. A data delay adjustment circuit group ( 110 ) is fed with data outputted from a flip-flop circuit group ( 106 ), adjusts a delay of the data so as to synchronize the operation of a data output terminal group ( 114 ) with the operation of a logic circuit ( 100 ), and outputs the data to the data output terminal group ( 114 ). A clock delay adjustment circuit ( 109 ) similarly adjusts a delay of a clock outputted from an inverter ( 105 ) and outputs the clock to a clock output terminal ( 113 ). Therefore, the operations of data output terminals are synchronized with the operation of the logic circuit ( 100 ) while keeping the phase relationship between an external output clock and external output data.
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