TRANSFORMER COUPLED CLOCK INTERFACE CIRCUIT FOR MEMORY MODULES
摘要
<p>The invention is a clock interface circuit for high-speed computer memory modules. It provides improved timing margin due to improved rise and fall times than achieved with present JEDEC specified clock distribution and timing networks. The invention also provides for improved clock and inverse clock symmetry around VREF.</p>
申请公布号
WO2006128049(A2)
申请公布日期
2006.11.30
申请号
WO2006US20597
申请日期
2006.05.25
申请人
THUNDER CREATIVE TECHNOLOGIES, INC.;WASHBURN, ROBERT, D.;MCCLANAHAN, ROBERT, F.
