发明名称
摘要 PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor chip capable of fining a wiring layer formed on a semiconductor element. SOLUTION: A laminate 10B at the upper part of a semiconductor chip 10 and a semiconductor element 10A at the lower part of the chip 10 are independently formed. The laminate 10B is collectively laminated on the element 10A, thereby forming the chip 10. In this way, since a through hole conductor 160 is arbitrarily formed, the aspect ratio of the conductor 160 can be made to be higher than that in conventional technique. Accordingly, the wiring layer provided on the chip 10 can be made finer.
申请公布号 JP3850260(B2) 申请公布日期 2006.11.29
申请号 JP20010328018 申请日期 2001.10.25
申请人 发明人
分类号 H01L23/12;H01L21/56;H01L21/60 主分类号 H01L23/12
代理机构 代理人
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