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发明名称
A pipeline analog-to-digital converter with correction of inter-stage gain errors
摘要
申请公布号
EP1441445(B1)
申请公布日期
2006.11.29
申请号
EP20030425033
申请日期
2003.01.24
申请人
STMICROELECTRONICS S.R.L.
发明人
CESURA, GIOVANNI;PANIGADA, ANDREA;BOSI, ALESSANDRO
分类号
H03M1/06;H03M1/16
主分类号
H03M1/06
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代理人
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