| 摘要 |
A semiconductor memory in which a drop in the potential of a bit line due to coupling capacitance at the time of writing data can be restored in a space-saving way without increasing a load at read time. In response to a selection signal, a selection circuit selects complementary bit lines and connects the selected complementary bit lines to write data bus lines or read data bus lines. When data is written, a voltage boosting circuit section selects a read data bus line connected to a bit line of the pair of complementary bit lines located opposite to a bit line the potential of which is decreased on the basis of the data to be written and raises the potential of the selected read data bus line. As a result, a potential level which has dropped due to coupling capacitance between the bit lines can be restored.
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